1. Field of the Invention
The present invention relates to a cache memory system in which a portion, of a cache memory, for obtaining a hit signal is improved.
2. Description of the Related Art
In general, a cache memory is constituted by a high-speed memory such as an SRAM, whereas a main memory is constituted by a relatively low-speed, large-capacity memory such as a DRAM. Of the data stored in the main memory, data which are used at high frequencies are also stored in the cache memory. Therefore, frequently used data are read out from the cache memory at high speed. Consequently, the total throughput of the system can be improved by using the cache memory.
A cache memory is generally constituted by a tag section for performing address detection, and a data section in which desired data is stored. The present invention is associated with the tag section.
In conventional cache memory system, a small amplitude signal read out from a memory core portion of the tag section is amplified first to the CMOS level by a sense amplifier. An address or index corresponding to an address in the main memory is stored in this memory core portion. The amplified signal is then compared with a signal (address), transmitted from a CPU, by a CMOS level comparator so as to determine whether the two signals coincide with each other. This determination result is input, as a tag match signal (corresponding to a hit signal, specifically a signal at a stage prior to the generation of a hit signal), to a hit logic. In the hit logic, a logical operation of the input tag match signal and a control bit signal is performed in a range of CMOS level. As a result, a hit signal is generated. For example, this control bit signal serves to invalidate the match signal when one data stored at one address in the main memory is different from the data stored at the corresponding address in the cache memory. A control bit signal is recorded as an attribute of each index stored in the memory core portion.
In the conventional cache memory system described above, a signal is amplified to the CMOS level (a full swing in the power-supply voltage range) by the sense amplifier, and is subsequently processed by the comparator and the hit logic. Therefore, the delay time before a hit signal is generated is determined by the operating speed (low speed because of a large amplitude) of a CMOS logic, and the number of gates through which a signal passes. In the CMOS logic, a high-speed, multi-input logical OR for hit detection is difficult to realize in terms of arrangement. In addition, if circuits such as a comparator and a hit logic are arranged by using long wires, the electrical wiring capacitance causes an increase in signal transfer delay time in the CMOS logic which handles a large-amplitude signal.